Integrated circuits in recent years have seen great advances in processing technology and photolithographic techniques, which has resulted in the ability to fabricate more complex and higher density devices. To realize these higher density devices, present technology has provided submicron line definition for defining the various structures on the integrated circuit. However, industry's need for increased density devices has far outdistanced the ability to realize this density with present techniques. This is due in part to the fact that most conventional processes utilize planar techniques with the structures defined in a two dimensional space.
In order to increase density with present processing technology and photolithographic techniques, process designers have resorted to vertical integration to more effectively utilize the available space. One vertical integration technique is to stack active devices on already processed devices. This stacking procedure requires the formation of a layer of silicon on the top of an already formed active device. A second level of active circuitry is then defined in this second layer. Although this type of technology significantly increases the density, it does present a problem with respect to forming contact holes and interconnects between the various levels in addition to increasing the complexity of the process.
Another vertical integration technique that has been successfully utilized is trenching whereby trenches are formed in the substrate and active circuits or capacitors formed on the sides and bottom of the trench. The trenching technology has come into widespread use with respect to dynamic random access memory cells having a density of one Megabit or more. Trenches can either be vertical wall trenches or "V" shape trenches for use with the VMOS technology. Although the vertical integration techniques have provided increased density, there are limitations to the present techniques.
The components that are most widely utilized in high density integrated circuits are the MOS transistor and the MOS capacitor. In order to improve operation of a capacitor, it is only necessary to increase its surface area or decrease the distance between the electrodes to increase capacity. Additionally, the depletion capacitance in a non-inversion type capacitor can be increased through use of an implanted region under the capacitor to provide the Hi-C capacitor. However, a transistor requires some additional considerations since there are numerous operational parameters to account for. For example, conventional MOS transistors have a width dimension which defines the overall width of the source and drain regions, and a length dimension which defines the channel length of the transistor. The operational parameters of the transistor are dependent on these geometries.
Typically, during fabrication of an MOS transistor, a moat is defined in a substrate with the width of the moat corresponding to the width of the transistor. A gate oxide layer and gate electrode are then deposited on the substrate along the full width of the transistor, the width of the gate electrode defining the channel length. Source and drain regions are then defined on either side of the gate along the entire width of the transistor. The dimensions of the source and drain regions perpendicular to the gate are selected for purposes of contacting thereto. In a planar structure, if a wider transistor is required, more two dimensional space is needed.
There are certain limitations on transistors which are size limited and which are a function of the width-to-length ratio. These are, for example, gain, speed and power handling capability. There are limits to scaling down these devices since scaling down may degrade performance. Thus far, the vertical integration process technology has not specifically addressed the transistor. Therefore, there exists a need for a process technology that will increase the packing density for a given transistor without unduly scaling down the device.